GTL (Gunning Transceiver Logic) is a logic type that is becoming increasingly popular. HSTL (High Speed Transistor Logic) is included within the GTL family. Both GTL and HSTL have a logic swing that is comparable to ECL (emitter-coupled logic), have relatively low power consumption, high speed, and do not require BICMOS. There are minor differences between the logic level voltages for GTL and HSTL. For example, the logic high level voltage for GTL may equal between 1.14 and 1.26 volts with a reference voltage of between 0.55 and 0.9, while the logic high level voltage for HSTL may equal between 1.4 volts and 1.6 with a reference voltage of between 0.68 and 0.9 volts. Note that a BICMOS circuit includes both bipolar and CMOS (complementary metal-oxide semiconductor) transistors on the same integrated circuit.
FIG. 1 illustrates in partial schematic diagram form and partial logic diagram form, prior art input stage 10 that receives a GTL level input signal and buffers and level converts the input signal to BICMOS levels. BICMOS logic levels swing from a logic high voltage equal to about a V.sub.BE (base-emitter diode voltage drop) below a positive power supply voltage, to a logic low voltage equal to about ground. Input stage 10 includes level shift circuit 12 and input buffer 14 and receives single-ended GTL level input signal A.sub.PAD, reference voltage V.sub.REF, and bias voltages N.sub.BIAS and A.sub.BIAS. In response, input stage 10 provides differential BICMOS level output signals A and A*. Note that an asterisk (*) after a signal name indicates that the signal is a logical complement of a signal having the same name but lacking the asterisk (*). Level shift circuit 12 includes P-channel transistors 16, 17, 21, and 22, NPN transistors 18 and 23, and N-channel transistors 19 and 24. Input buffer 14 includes load network 26, NPN transistors 27 and 28, N-channel transistor 29, and inverters 31 and 32. Differential amplifier 25 comprises load network 26, NPN transistors 27 and 28, and N-channel transistor 29. Input stage 10 is supplied with a power supply voltage equal to about 3 volts.
Reference voltage V.sub.REF is externally provided by the user, and is typically set at the midpoint of a logic swing of input signal A.sub.PAD. If the voltage of input signal A.sub.PAD is lower than the voltage of reference voltage V.sub.REF, then more current is steered through NPN transistor 28 than through NPN transistor 27, and output signal A* is a logic high voltage and output signal A is a logic low voltage. If the voltage of input signal A.sub.PAD is higher than the voltage of reference voltage V.sub.REF, then more current is steered through NPN transistor 27 than through NPN transistor 28, and output signal A* is a logic low voltage and output signal A is a logic high voltage.
An input stage, such as prior art input stage 10, must function through a range of possible voltages for the various input signals. NPN transistors 18 and 23 of level shift circuit 12 function to lower the voltages of input signal A.sub.PAD and reference voltage V.sub.REF before applying them to NPN transistors 27 and 28. This allows input stage 10 to function properly for relatively low values of reference voltage V.sub.REF. However, input stage 10 is not able to operate adequately for relatively high values of V.sub.REF. For example, when reference voltage V.sub.REF is equal to about one volt, P-channel transistors 17 and 22 cannot be biased properly with a power supply voltage (V.sub.DD) equal to about 3 volts. In addition, bias voltage A.sub.BIAS is required to follow V.sub.DD, complicating circuit design of an A.sub.BIAS generation circuit.